With the continuous reduction in size of a semiconductor device, enhancing the carrier mobility of channel becomes a very important technique. In the design of a stress layer of a substrate, different materials have different characteristics such as lattice constant, dielectric constant, forbidden gap, particularly carrier mobility, etc., as shown in Table 1 below.
TABLE 1LatticeDielectricForbidden Mobility (cm2/V-s)Materialconstant (nm)constantgap(eV)electronholeSi0.543111.81.121600430Ge0.5675160.6639001900GaAs0.565312.41.429200400InAs0.605814.80.3640000500InSb0.64817.70.1777000850
It can be seen from Table 1 that among the above possible materials for substrate, Ge has the highest hole mobility and a relatively higher electron mobility, thus can make the performance of the PMOS taking it as the channel region best and the performance of the NMOS good. Using Ge as the substrate of a semiconductor device will greatly enhance the carrier mobility, thus enabling manufacture of a higher-speed large scale integrated circuit (LSIC). Similarly, using InSb as the channel of NMOS can maximum the performance of the NMOS, meanwhile the performance of PMOS of InSb is also good.
Further, it can also be seen from Table 1 that materials Ge and GaAs have a similar lattice constant as that of the material Si, thus they can be easily integrated on a Si substrate commonly used in the semiconductor technology, such that a semiconductor device with better performance can be manufactured by the technology without making great improvements thereto, thereby improving the performance while reducing the cost at the same time. However, certain disparity exists between the lattice constant of InAs and InSb and that of the material Si, a transition layer or a buffer layer, which may be made of GaAs and GaN etc. with a lattice constant similar to that of Si shall be added when materials of InAs and InSb are used.
In the design of a semiconductor device and an integrated circuit thereof, generally a shallow trench isolation (STI) is used to manufacture the insulating isolation among a plurality of devices in the substrate. The known method for manufacturing a STI comprises first etching a trench in the substrate, then depositing an insulating film made of e.g., an oxide in the formed trench by a process such as chemical vapor deposition (CVD). With reduction in the device size, the aspect ratio of corresponding STI becomes larger continuously and the step coverage of the oxide insulating film becomes poorer, that is, the oxide insulating film on top of the narrower trench may join earlier while the trench below is not completely filled, thus holes or gaps may exist in the STI, resulting in that the insulating property of the device deteriorates and reliability thereof becomes worse.
Overall, the existing semiconductor device with Si channel surrounded by STI has poor performance and reliability, the carrier mobility in the channel region shall be further improved and holes in STI shall be removed to improve the electrical performance and reliability of the semiconductor device.